1. Field of the Invention
The present invention relates to a mask used in a charged particle beam projecting apparatus adapted to project respective patterns of a plurality of regions, which plurality of regions are formed in a mask, on a substrate by means of a charged particle beam, so as to project a desired pattern on the substrate. This invention is also concerned with a method for dividing the pattern to be projected on the substrate.
2. Description of Related Art
A known lithography apparatus for forming an integrated circuit pattern on a semiconductor wafer comprises a charged particle beam projecting apparatus wherein a mask having a certain pattern formed therein is irradiated with a charged particle beam, such as an electron beam, and a portion of the pattern in the irradiated range of the mask is projected in a reduced ratio on the wafer by means of a projecting lens. In this type of projecting apparatus, the entire area of the mask cannot be simultaneously irradiated with the charged particle beam, and therefore the field of view of an optical system is divided into a multiplicity of small regions, so as to project a pattern image that is also divided into small sections. Such an apparatus is disclosed, for example, in U.S. Pat. No. 5,260,151.
FIGS. 5A and 5B are perspective views schematically showing the relationship between a pattern of a mask 1 to be projected, and a pattern projected on a wafer 2. The appearance of the wafer 2 as a whole is shown in FIG. 5A, and a "Va" region of this wafer 2 is shown in enlargement in FIG. 5B. As shown in FIG. 5B, the mask 1 has a plurality of rectangular small regions 1a, and a boundary region 1b that provides partition in a grid form for defining these small regions 1a. In each of the small regions 1a of the mask 1, there is formed a section of a pattern (which will be described later) to be projected on a region 2a of the wafer 2 that corresponds to one chip (one piece of semiconductor). The boundary region 1b is formed uniformly of a material that interrupts or largely scatters the charged particles of the incident beam. The charged particle beam is formed into a cross sectional shape (rectangular shape) similar to that of the small region 1a, and is directed at one of the small regions 1a of the mask 1 by means of a deflector for selecting the field of view (not shown). The charged particle beam BM that has passed the small region 1a passes a crossover CO on an optical axis AX by means of a projecting lens (not shown), and is incident upon a unit region 2b within a chip region 2a of the wafer 2. In this manner, the image of the pattern formed in the small region 1a of the mask 1 is projected in a reduced ratio on the unit region 2b of the wafer 2.
FIG. 6A shows a part of a projected pattern 3 to be projected on the wafer 2, and FIG. 6B shows a part of a mask pattern formed in some of the small regions 1a of the mask 1. The projected pattern 3 consists of pattern elements P11, P12 . . . , and is divided by parting lines d1 indicated by dashed lines into a plurality of block patterns 3aa, 3ab . . . which are to be projected on the wafer 2. On the other hand, small regions 1aa, 1ab . . . of the mask 1 are identical with the small regions 1a shown in FIG. 5B. The pattern elements included in the block pattern 3aa are formed in the small region 1aa of the mask 1, and the pattern elements included in the block pattern 3ab are formed in the small region 1ab. Conventionally, the projected pattern 3 is routinely divided into the rectangular block patterns 3aa, 3ab . . . , as shown in FIG. 6A and FIG. 6B, irrespective of the shape of the pattern elements P11, P12 . . . of the projected pattern 3.
With the projected pattern 3 routinely divided into the block patterns as described above, some of the pattern elements intersect the parting lines such that each of these intersecting pattern elements extends over two block patterns. For example, the pattern element P22 intersects the parting line d1 of the projected pattern 3, and is thus included in both of the block patterns 3aa and 3ab, as shown in FIG. 6A, so that the element P22 is split into two pattern elements P22a, P22b that are respectively formed in the small regions 1aa and 1ab of the mask 1, as shown in FIG. 6B. Since the pattern element P22 is projected onto the wafer 2 by respectively projecting the pattern elements P22a, P22b, a connecting portion on the wafer 2 between these pattern elements P22a, P22b inevitably suffers from connection error. If the pattern element P22 corresponds to a drain layer of a MOS transistor, for example, such connection error occurring in the wafer 2 may result in changes in characteristics of the MOS transistor and reduced yield of the device.
Further, when the block patterns 3aa, 3ab are formed in the small regions 1aa, 1ab of the mask, the area having z width where the block patterns 3aa, 3ab can not be formed is needed between the small regions 1aa, 1ab to ensure the physical strength of the mask 1. If the size of a semiconductor device is assumed as 18.times.36 mm.sup.2 and a size of the area corresponding to one of the small regions of the mask is assumed as 0.25.times.0.25 mm.sup.2, a problem arises that the size of the mask becomes bigger so that longitudinal length increases by (72.times.z) and lateral length increases by (144.times.z).